Beschrijving
| 1. | Multiple stages of regulation for SPDIF input receiver, USB input, clock oscillator, DAC and output stage for accurate output. |
| 2. | Very clean master clock to SPDIF input receiver and USB input to ensure low jitter operation. |
| 3. | Discrete filter and output stage for optimum performance (no Op-Amp ICs). |
| 4. | Digital output can be switched “on” or “off” (and is re-timed) to reduce the jitter level as compared to SPDIF input. This function can also be used to convert USB input to SPDIF output. |
